Silicon on sapphire wafers technology refers to growing a layer of silicon thin film on the epitaxy of sapphire wafer to make semiconductor integrated circuit, short for SOS wafer.
This structure can provide ideal isolation and reduce the parasitic capacitance at the bottom of the PN junction, so it is suitable for manufacturing high-speed LSI to achieve high speed and low power consumption. CMOS circuits (see complementary metal-Oxide-semiconductor integrated circuits), namely CMOS/SOS circuits, are generally made by this process. The crystalline direction of sapphire used for silicon on sapphire wafers is (1T02), and that of silicon epitaxial film is (100). The film thickness is about 0.5 micron. There are two methods for producing CMOS/SOS IC: deep depletion type and double enhancement type.
(1) It can eliminate the bottom capacitance of PN junction from source and leakage area, and the parasitic capacitance of metal interconnect line is also greatly reduced, so the circuit speed is higher and the average power consumption is also reduced.
(2) The isolation between devices is ideal, without isolation trap and channel cut-off ring, is conducive to improve the density of integration.
(3) There is no bulk silicon under the field oxide, which avoids field reverse leakage caused by radiation. Therefore, CMOS/SOS integrated circuits can be made into radiation-resistant integrated circuits suitable for aviation and nuclear radiation environment.
(4) It can eliminate parasitic PNPN brake flow, thus eliminating the usual latch effect in CMOS.
